Generally, when there is any defect such as faulty connection in a memory cell of an SRAM, data at H-level written in the memory cell may sometimes be lost during the passage of a long period of time. In order to test for such a defect, there is executed a test (retention test) by writing H-level data in a memory cell and reading out the data from the memory cell after a specified period of time passes to check whether H-level data is retained. It should be noted that description is made based on the positive logic in the specification unless otherwise specified.
FIG. 12 is a circuit diagram showing a portion of circuit configuration of an SRAM based on the conventional technology. Although FIG. 12 shows four memory cells, each of which is of a CMOS type, in an actual case, each of the memory cells is arranged in a M.times.N (M and N are integers) matrix. The memory cell 1 comprises access transistors Q1, Q2 used as switches for connection to the bit lines 2, 3; and P channel and N channel transistors Q3, Q4, Q5, Q6 constituting a pair of CMOS inverters of a flip-flop.
The source and drain of the access transistor Q1 are connected to the bit line 2 as well as to an input of one of CMOS inverters and a gate thereof is connected to a word line 4. The source and drain of the access transistor Q2 are connected to the bit line 3 as well as to an input of the other CMOS inverter and a gate thereof is connected to the word line 4. Each output of the pair of CMOS transistors is connected to an input of the other CMOS transistor respectively. When a potential at the word line 4 connected to the memory cell 1 becomes H-level, the access transistors Q1, Q2 of this memory cell 1 enter into ON state, the flip-flop comprising the transistors Q3, Q4, Q5, and Q6 is connected to the bit lines 2, 3, data is written in this flip-flop, and the written data is retained.
The bit lines 2, 3 are connected to a write driver 5 as well as to a sense amplifier (SA) 6 via selector transistors Q7, Q8 as switches for selecting the bit lines 2, 3 respectively. The sense amplifier 6 is connected to a data output (DO) terminal 8 via a data output buffer 7. Gates of the selector transistors Q7, Q8 are connected to a column address decoder 9. The column address decoder 9 is connected to a column address input (An to Am) terminal 11 via a column address buffer 10. In addition, the bit lines 2, 3 are connected to transistors Q9, Q10 as resistors respectively. The word line 4 is connected to a row address decoder 12. The row address decoder 12 is connected to a row address input (A1 to An-1) terminal 14 via a row address buffer 13.
FIG. 13 shows a configuration of the write driver 5. The write driver 5 is configured with a write-driver control circuit 20 (Refer to FIG. 12) comprising two dual-input NAND gates 21, 22, two dual-input NOR gates 23, 24, and three inverters 25, 26, and 27 as well as with P channel and N channel transistors Q11, Q12, Q13, and Q14 constituting a pair of CMOS inverters. The write driver 5 is connected to a data input (DI) terminal 28 as well as to a write enable (WE) terminal 29.
The data input terminal 28 is connected to a first input terminal of the NAND gate 21 as well as to a first input terminal of the NOR gate 23, and also connected to a first input terminal of the other NAND gate 22 as well as to a first input terminal of the NOR gate 24 via the inverter 25. The write enable terminal 29 is connected to second input terminals of the NOR gates 23, 24, and also connected to second input terminals of the NAND gates 21, 22 via inverters 26 and 27 respectively.
Output terminals of the NAND gate 21 and NOR gate 23 are connected to gates of the P channel transistor Q11 and the N channel transistor Q12, and an output signal from a CMOS inverter formed with the pair of transistors Q11, Q12 is supplied to the bit line 2. Output terminals of the NAND gate 22 and NOR gate 24 are connected to gates of the P channel transistor Q13 and the N channel transistor Q14, and an output signal from a CMOS inverter formed with the pair of transistors Q13, Q14 is supplied to the other bit line 3.
FIG. 14 explains the operations of the write driver 5. When the write enable signal WE is "0" and the input data signal DI is "0", mode of writing L-level data in the memory cell 1 is effected, and signals outputted to the bit line 2 and the bit line 3 are "0" and "1" respectively. When the write enable signal WE is "0" and the input data signal DI is "1", mode of writing H-level data in the memory cell 1 is effected, and signals outputted to the bit line 2 and the bit line 3 are "1" and "0" respectively. When the write enable signal WE is "1", data reading mode is effected, and both of the bit line 2 and bit line 3 enter a high impedance state ("Z").
Let us consider a case, as shown in FIG. 15, in which the connection between the source of the P channel transistor Q3 as a load transistor in the memory cell 1 and the power terminal is faulty. In such a case, in the conventional type of SRAM described above, if H-level data is written in the memory cell 1, charge supplied from the write driver 5 is accumulated, immediately after the data is written, at a drain of the transistor Q3 (point B in FIG. 15), namely at an output point of the CMOS inverter including the transistors Q3, Q4. Therefore, the memory cell 1 retains H-level data.
However, the charge accumulated at the point B disappears due to leakage in association with the passage of time. On the other hand, charge is not supplied from the transistor Q3, so that the memory cell 1 becomes unstable. If data is read from such a memory cell 1, the same data as the written data, namely ordinary data can be read immediately after the data is written, but faulty data is read after the passage of a long period of time. Therefore, a retention test has to be carried out after a prespecified period of time since data is written, which disadvantageously requires a longer time for testing.